A Survey of Clock Distribution Techniques Including Optical and RF Networks

Clock distribution has become an increasingly challenging problem for VLSI designs, consuming an increasing fraction of resources such as wiring, power, and design time. Power consumption of up to 40% 50% has been reported on clock distribution. Unwanted differences or uncertainties in clock network delays degrade performance or cause functional errors. Although there are lots of other techniques and research in clock distribution networks, in this report a detailed study of wireless and optical clock distributions is performed and compared with the conventional clock distribution technique. These techniques employ either transmitter/receiver or optical fiber to distribute clock signal to entire chip, so that there is a reduction in interconnecting wires which reduces the total load capacitance of the clock distribution network. Finally some future work is discussed on these techniques.